Optimization of semiconductor devices continues to be an important goal for the semiconductor industry. The continued miniaturization of semiconductor devices, such as bipolar transistors, presents ongoing challenges to semiconductor manufacturers in maintaining or improving that optimization while maintaining product yields and minimizing production time and costs. One such challenge resides in reducing boron penetration associated with bipolar transistors that are located on the same chip as standard CMOS transistors.
As performance requirements have continued to increase, leakage and threshold voltage concerns have become more important to semiconductor manufacturers and attention has begun to focus on how to decrease leakage and maintain threshold voltages. In some semiconductor device configurations, bipolar transistor and CMOS transistors are often located on the same chip and process flows are configured to achieve and integrated design flow to build both bipolar transistors and CMOS transistors on the same chip. In such instances, protective films, such as a polysilicon and nitride stack, are often deposited over the CMOS region to protect it from the fabrication processes used to build the bipolar transistors.
When constructing a bipolar device in a BICMOS process flow, the CMOS region needs to be protected. Conventional methods use a nitride film or a stack of polysilicon and nitride as protective layers. During the actual nitride deposition step and subsequent heat treatments, hydrogen can diffuse from the nitride film down through the PMOS poly gate and into the gate oxide, where it acts to terminate non-bridging silicon atoms. These terminations tend to be weaker bonds, allowing the boron to mover more easily through the oxide substitutionally. The result is boron penetration through the gate oxide and into the underlying silicon. This can cause device threshold to drop and negatively affect device performance. The problem of boron penetration has become more acute as the thickness of the gate oxides has decreased below 3.0 nm.
Accordingly, there is a need to provide a process and device by which boron penetration is reduced in the CMOS region.